11.02.2021 -- The purpose of this lab is to build and test a Hartley oscillator in LTSpice and then to breadboard and test it as well. An oscillator takes a flat DC signal and oscillates it so that a sine wave is formed.
9.1 LTSpice Simulation
1-3) When the loop gain is too high, there is clipping at the bottom of the output sine wave. See below in Figure 9.1 for the clipping distortion.
Figure 9.1 Vout signal from default Hartley Oscillator
4-7)
Table 9.1 LTSpice Simulation Data
9.2 Building/Testing the Oscillator
The circuit in Figure 9.3 is constructed.
Figure 9.2 Oscillator circuit
Figure 9.3 Another Oscillator Scope
When testing for the high and low frequency, there is a point where the frequency started to change directions. These values are recorded in Table 9.2.
| comments | |
f hi | 1.66 MHz | output signal @ 9.00 Vpp |
f lo | 1.03 MHz | output signal @ 8.2 Vpp |
Table 9.2 High and Low Frequencies
Conclusion
I was able to get my circuit working properly after fixing some connections in the circuit. At first, the circuit would not output an oscillating signal because I had constructed the circuit in 9.2. I found it interesting that there was a certain range of frequencies and peak-to-peak voltages that the signal will stay within.
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